ICS1894-32 Datasheet, PDF (3/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
TP_AP
TP_AN
VSS
VDD
TP_BN
TP_BP
VDD
TCSR
9
VSS
10
RESET_N
11
P2/INT
12
MDIO
13
MDC
14
AMDIX/RXD3
15
P3/RXD2
16
RXTRI/
RXD1
17
FDPX/
RXD0
18
RMII/RXDV
19
VDDIO
20
ANSEL/
RXCLK
21
NOD/
RXER
22
SPEED/
TXCLK
23
TXEN
24
TXD0
25
VDDD
26
TXD1
27
TXT2
28
TXD3
Pin
Type¹
Pin Description
AIO Twisted pair port A (for either transmit or receive) positive signal
AIO Twisted pair port A (for either transmit or receive) negative signal
Ground Connect to ground.
Power 3.3V Power Supply
AIO Twisted pair port B (for either transmit or receive) negative signal
AIO Twisted pair port B (for either transmit or receive) positive signal
Power 3.3V Power Supply
AIO Transmit Current bias pin, connected to Vdd and ground via resistors (see
“Recommended Component Values” table and the “ICS1894-32 TCSR” figure).
Ground Connect to ground.
Input Hardware reset for the entire chip (active low)
IO/Ipd PHY address Bit 2 as input (during power on reset/hardware reset)
Interrupt output as output (default active low, can be programmed to active high)
IO Management Data Input/Output
Input Management Data Clock
IO/Ipu AMDIX enable as input (during power on reset/hardware reset)
Receive data Bit 3 in MII mode as output.
IO/Ipd PHY address Bit 3 as input (during power on reset/hardware reset)
Receive data Bit 2 in MII mode as output.
IO/Ipu RX tri-state enable as input (during power on reset/hardware reset)
Receive data Bit 1 in both RMII and MII mode as output.
IO/Ipu Full duplex enable as input (during power on reset/hardware reset)
Receive data Bit 0 in both RMII and MII mode as output
IO/Ipd RMII/MII select as input (during power on reset/hardware reset)
Receive data valid in MII mode and CRS_DV in RMII mode as output.
Power 3.3 V/1.8 V IO Power Supply.
IO/Ipu Auto-negotiation enable as input (during power on reset/hardware reset)
Receive clock in MII mode as output.
IO/Ipd Node/repeater select as input (during power on reset/hardware reset)
Receive error in MII/RMII mode as output
IO/Ipu 10M/100M select as input (during power on reset/hardware reset)
Transmit clock in MII mode as output
Input Transmit enable in RMII/MII mode
Input Transmit data Bit 0 in RMII/MII mode
Power 3.3 V Power Supply
Input Transmit data Bit 1 in RMII/MII mode
Input Transmit data Bit 2 in MII mode
Input Transmit data Bit 3 in MII mode
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 3
ICS1894-32 REV F 110209