ICS1894-32 Datasheet, PDF (38/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
10M Media Independent Interface: Receive Latency
The table below lists the significant time periods for the 10M MII timing. The time periods consist of timings of
signals on the following pins:
• TP_RX (that is, the MII TP_RXP and TP_RXN pins)
• RXCLK
• RXD
The 10M MII Receive Latency Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter
t1 First Bit of /5/ on TP_RX to /5/D/ on RXD
Conditions Min. Typ. Max. Units
10M MII
– 6.5 7 Bit times
10M MII Receive Latency Timing Diagram
TP_RX^†
RXCLK
RXD
5
5
t1
† _{Manchester encoding is not shown.}
5
D
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 38
ICS1894-32 REV F 110209