ICS1894-32 Datasheet, PDF (42/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)
The table below lists the significant time periods for the 10M MII carrier assertion/de-assertion during half-duplex
transmission. The time periods consist of timings of signals on the following pins:
• TXEN
• TXCLK
• CRS
The 10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) shows the timing diagram for
the time periods.
Time
Period
Parameter
t1 TXEN Asserted to CRS Assert
t2 TXEN De-Asserted to CRS De-Asserted
Conditions Min. Typ. Max. Units
0
–
2 Bit times
0
2
4 Bit times
10M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only)
t2
TXEN
TXCLK
CRS
t1
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 42
ICS1894-32 REV F 110209