ICS1894-32 Datasheet, PDF (46/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Reset: Hardware Reset and Power-Down
The table below lists the significant time periods for the hardware reset and power-down reset. The time periods
consist of timings of signals on the following pins:
• REFIN
• RESETn
• TXCLK
The Hardware Reset and Power-Down Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter
t1 RESETn Active to Device Isolation and Initialization
t2 Minimum RESETn Pulse Width
t3 RESETn Released to TXCLK Valid
Conditions
–
–
–
Min. Typ. Max Units
.
– 60 –
ns
200
–
ns
– 35 500 ms
Hardware Reset and Power-Down Timing Diagram
REFIN
RESETn
t1
t2
t3
TXCLK Valid
Power
Consumption
(AC only)
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 46
ICS1894-32 REV F 110209