ICS1894-32 Datasheet, PDF (36/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
10M MII Synchronous Transmit Timing Diagram
PHYCEIVER
TXCLK
TXD[3:0]
TXEN
TXER
t1
t2
100M/MII Media Independent Interface: Synchronous Receive Timing
The table below lists the significant time periods for the MII/100M Stream Interface synchronous receive timing. The
time periods consist of timings of signals on the following pins:
• RXCLK
• RXD[3:0]
• RXDV
• RXER
The MII Interface: Synchronous Receive Timing figure shows the timing diagram for the time periods.
Time
Period
Parameter
t1 RXD[3:0], RXDV, and RXER Setup to RXCLK Rise
t2 RXD[3:0], RXDV, and RXER Hold after RXCLK Rise
Min. Typ. Max. Units
10.0 –
10.0 –
–
ns
–
ns
MII Interface: Synchronous Receive Timing
RXCLK
RXD[3:0]
RXDV
RXER
t1
t2
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 36
ICS1894-32 REV F 110209