ICS1894-32 Datasheet, PDF (45/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Reset: Power-On Reset
The table below lists the significant time periods for the power-on reset. The time periods consist of timings of
signals on the following pins:
• VDD
• TXCLK
The Power-On Reset Timing Diagram shows the timing diagram for the time periods.
Time
Period
Parameter
t1 VDD ≥ 2.7 V to Reset Complete
Conditions Min. Typ. Max. Units
–
40 45 500 ms
Power-On Reset Timing Diagram
VDD
2.7 V
t1
TXCLK
Valid
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 45
ICS1894-32 REV F 110209