ICS1894-32 Datasheet, PDF (4/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE

ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pin
Number
29
30
31
32
PADDLE
Pin
Name
REFOUT
REFIN
P0/LED0
P1/LED1
VSS
Pin
Type¹
Pin Description
Output 25 MHz crystal output, floating in RMII mode
Input 25 MHz crystal (or clock) input in MII mode. 50 MHz clock input in RMII mode.
IO PHY address Bit 0 as input (during power on reset/hardware reset) and LED # 0
(function configurable, default is "activity/no activity") as output
IO PHY address Bit 1 as input (during power on reset/hardware reset) and LED # 1
(function configurable, default is "10/100 mode") as output
Ground Connect to ground.
Notes:
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents
valid data to MAC on the MII interface. RXD[3..0] is invalid when RXDV is de-asserted.
3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid
data from the MAC on the MII interface. TXD[3..0] has no effect when TXEN is de-asserted.
5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
IDT™ / ICS™ 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4
ICS1894-32 REV F 110209