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ICS1894-32 Datasheet, PDF (15/53 Pages) Integrated Device Technology – 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE | |||
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Pins for Monitoring the Data Link table
Pin
P0/LED0
P1/LED1
Status Events that drive the LEDs
Link, Activity, Tx, Rx, COL, Mode, Dplx
Link, Activity, Tx, Rx, COL, Mode, Dplx
Note:
1. During either power-on reset or hardware reset, each
multi-function configuration pin is an input that is sampled
when the ICS1894-32 exits the reset state. After sampling is
complete, these pins are output pins that can drive status
LEDs.
2. A software reset does not affect the state of a
multi-function configuration pin. During a software reset, all
multi-function configuration pins are outputs.
3. Each multi-function configuration pin must be pulled
either up or down with a resistor to establish the address of
the ICS1894-32. LEDs may be placed in series with these
resistors to provide a designated status indicator as
described in the Pins for Monitoring the Data Link table. Use
1K⦠resistors.
Caution: Pins listed in the Pins for Monitoring the Data Link
table must not float.
4. As outputs, the asserted state of a multi-function
configuration pin is the inverse of the sense sampled during
reset. This inversion provides a signal that can illuminate an
LED during an asserted state. For example, if a
multi-function configuration pin is pulled down to ground
through an LED and a current-limiting resistor, then the
sampled sense of the input is low. To illuminate this LED for
the asserted state, the output is driven high.
5. Adding 10K⦠resistors across the LEDs ensures the PHY
address is fully defined during slow VDD power-ramp
conditions.
6. PHY address 00 tri-states the MII interface. (Do not select
PHY address 00 unless you want the MII tri-stated.)
The following figure shows typical biasing and LED connections for the ICS1894-32.
ICS1894CK-32
P1/LED1
32
P0/LED0
31
LED1 10Kâ¦
1Kâ¦
VDD
1Kâ¦
LED0 10Kâ¦
The above circuit decodes the PHY address = 1
IDT⢠/ ICS⢠10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 15
ICS1894-32 REV F 110209
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