IC-NG Datasheet, PDF (9/21 Pages) IC-Haus GmbH – 8-BIT Sin/D CONVERTER-PROCESSOR

iC-NG
8-BIT Sin/D CONVERTER-PROCESSOR
Rev D3, Page 9/21
Interfaces
The chip must be configured for the application in use
after being switched on and after every reset. The set-
tings and output values are stored in registers in iC-
NG.
There are various ways of accessing these registers.
If a serial EEPROM (e.g. SDA 2516, ST24CO2) is
con-nected to pins SDA and SCL, all parameters will
be read in automatically from there. The access mode
is also determined by the EEPROM (ACCMOD(1:0)).
first access and the date by the second. The internal
address register is automatically increased by one
after each write. The registers of successive ad-
dresses can thus be easily written without having to
reload the address register. A write cycle to address
10 and a subsequent read out are indicated in Figure
9.
In the absence of an EEPROM, the access mode is
set directly by pins SDA and SCL, which are equipped
with internal pull-up resistors. Three modes are sup-
ported:
Fig. 9: write access to address 10 and subsequent
read out.
SDA SCL Access Mode (no EEPROM)
0
0 Parallel absolute mode
1
0 Serial mode
1
1 Incremental mode
Fig. 7: access modes
1. Parallel-absolute mode
This mode is suitable for using iC-NG as peripheral
chip in an 8-bit bus system. The registers can be ac-
cessed via the data ports D0 to D7, controlled by read
/ write access inputs NWR and NRD. The two pins
should not simultaneously receive low level.
Addressing is controlled via an internal address regis-
ter and a status machine. The internal status (A or B)
determines whether write access affects the address
register or a data register addressed by it. The chip is
in status A after a reset and each read, and in status B
after each write (Figure 8).
Read access
For a read cycle, the register address is also given first
(write access), the data content then being read out
with NRD at low.
The length of the output value is set to 1..4 bytes with
the OUTSEL(1:0) registers. OUTSEL also influences
the content of the internal address counter after a
read. It is not increased if the length of the output
value is set to one byte. Other settings reset the ad-
dress counter to zero after the highest byte of the out-
put value has been read, otherwise it is increased by
one.
The outputs remain constant during the read process,
even if the relevant register changes (except incre-
mental signals and interrupt and error status).
The NG, COUNT and TACHO registers are again stor-
ed with the falling edge at NRD if OUTSEL has been
programmed to zero or the address counter is at zero.
It is thus possible to read a 4-byte output value in four
accesses.
The interval between two consecutive pulses to NRD
or NWR must be at least 3 clock cycles. The cyclic
read out of a 2-byte output value (OUTSEL(1:0)= 1) is
shown in Figure 10.
Fig. 8: status control.
Write access
The data to be written is applied to pins D0 to D7 and
a low pulse to NWR. The data is accepted with the
rising edge at NWR. A write cycle consists of at least
two accesses. The register address is given by the
Fig. 10: cyclic read out of the output value (16-bit).