IC-NG Datasheet, PDF (17/21 Pages) IC-Haus GmbH – 8-BIT Sin/D CONVERTER-PROCESSOR

iC-NG
8-BIT Sin/D CONVERTER-PROCESSOR
Rev D3, Page 17/21
Hysteresis, Data Shift, PGA Bypass
Bit
Name
7
NGLJ
6
ADAP
5
HYS5
4
HYS4
3
HYS3
2
HYS2
1
HYS1
Adr: 8
0
HYS0
Hysteresis
Bit 5:0
HYS(5:0)
'00'h
..
'3F'h
Data Shift
Bit 6
0
ADAP
1
PGA Bypass
Bit 7
0
NGLJ
1
Hysteresis according to the tables on page 11
Programmable gain amplifier (PGA) deactivated
Programmable gain amplifier (PGA) activated
Output value is justified right
Output value is shifted left (only practical in synchronous-serial mode for resolutions smaller than 136)
Z Index Position, Counter Depth, Operation Mode
Bit
Name
7
6
5
4
3
ACCMOD1 ACCMOD0 OUTSEL1 OUTSEL0 ZCONF3
2
ZCONF2
Adr: 9
1
0
ZCONF1 ZCONF0
Z Index Position
Bit 2:0
ZCONF(2:0)
000
001
010
011
100
101
110
111
Bit 3
0
ZCONF3
1
Counter Depth
Bit 5:4
00
OUTSEL(1:0) 0 1
10
11
Operation Mode
Bit 7:6
00
ACCMOD(1:0) 1 0
11
01
Zero crossing at 0°
Zero crossing at 45°
Zero crossing at 90°
Zero crossing at 135°
Zero crossing at 180°
Zero crossing at 225°
Zero crossing at 270°
Zero crossing at 315°
(Sin = 0, COS = 1)
(Sin = COS > 0)
(Sin = 1, COS = 0)
(Sin = -COS > 0)
(Sin = 0, COS = -1)
(Sin = COS < 0)
(Sin = -1, COS = 0)
(Sin = -COS < 0)
(ZX, Z4 both ½ cycle wide)
(ZX,Z4 both ¼ cycle wide)
(ZX,Z4 both ½ cycle wide)
(ZX,Z4 both ¼ cycle wide)
(ZX,Z4 both ½ cycle wide)
(ZX,Z4 both ¼ cycle wide)
(ZX,Z4 both ½ cycle wide)
(ZX,Z4 both ¼ cycle wide)
If the ZERO inputs do not receive a true zero signal from the sensor, different wiring is necessary to pro-
duce ZERO = 1 (via V(PZERO) > V(NZERO)).
Z4 gated with A4 and B4 (width of Z4 = ¼), Z4 gated with A4 or B4 (width of Z4 = ½)
Z4 not gated
Output value consists of NG(7:0)
Output value consists of COUNT(7:0) & NG(7:0)
Output value consists of COUNT(15:0) & NG(7:0)
Output value consists of COUNT(23:0) & NG(7:0)
This setting affects target position evaluation and sets the MSB to synchronous-serial mode
Parallel mode
Synchronuous-serial mode
Incremental mode
not permitted
The access mode is determined when the configuration is loaded from the serial EEPROM and cannot be
altered during operation. If no EEPROM is available, the access mode can be set via pins SDA and SCL.