IC-NG Datasheet, PDF (19/21 Pages) IC-Haus GmbH – 8-BIT Sin/D CONVERTER-PROCESSOR

iC-NG
8-BIT Sin/D CONVERTER-PROCESSOR
Input Amplifier Compensation
Bit
Name
7
6
5
4
CZERO3 CZERO2 CZERO1 CZERO0
3
CSIN3
SIN, COS Inputs
Bit 3:0
'0'h
CSIN(3:0)
..
'F'h
ZERO Input
Bit 7:4
'0'h
CZERO(3:0) ..
'F'h
0.0pF
0.8pF / LSB
12.0pF
0.0pF
0.8pF / LSB
12.0pF
2
CSIN2
Rev D3, Page 19/21
1
CSIN1
Adr: 12
0
CSIN0
Clock Frequency Select
Bit
7
Name
6
5
4
3
FREQ
2
reserved
1
reserved
Adr: 13
0
reserved
Bit 3
0
FREQ
1
Bit 2:0
0
reserved
Clock frequency has increased ca. tenfold (only valid when no external clocking pulse is fed in)
Clock frequency not multiplied
Registers must always be programmed to 0
PGA Gain (write only)
Bit
Name
7
G7[i]
6
G6[i]
5
G5[i]
4
G4[i]
3
G3[i]
Bit 7:0
G(7:0)[i]
'00'h
'01'h
..
'7F'h
'FF'h
..
'81'h
'80'h
255/128 . 1.992
. 1.984
1/128 pro LSB ×0.0078
128/128 = 1
255/255 = 1
. 0.50592
1/255 pro LSB ×0.00392
128/255 . 0.502
2
G2[i]
Adr: 16-23 (1.-8. Segment)
1
G1[i]
0
G0[i]
PGA Offset (write only)
Bit
Name
7
O7[i]
6
O6[i]
5
O5[i]
4
O4[i]
3
O3[i]
Bit 7:0
O(7:0)[i]
'00'h
..
'7F'h
'FF'h
..
'80'h
-127/384×A . -0.33×A
-1/384×A pro LSB
-0/384×A = 0
0/384×A = 0
1/384×A pro LSB
127/384×A . 0.33×A A = input signal amplitude
2
O2[i]
Adr: 24-31 (1.-8. Segment)
1
O1[i]
0
O0[i]