IC-NG Datasheet, PDF (10/21 Pages) IC-Haus GmbH – 8-BIT Sin/D CONVERTER-PROCESSOR

iC-NG
8-BIT Sin/D CONVERTER-PROCESSOR
Rev D3, Page 10/21
2. Synchronous-serial mode with 33-bit format
Resolution RES(4:0) and RES(6,5)
In this mode, communication is via a synchronous two-
wire connection. The registers cannot be accessed;
only the output value and the error bit are transmitted.
The two-wire connection exists of a clock input (NRD)
and a data output with driver at NWR. Data transmis-
sion is controlled externally by the clock line.
The output value is latched with the first falling edge at
NRD. With every subsequent rising edge the output
value is serially output to NWR in binary code, begin-
ning with the MSB set by OUTSEL. The error bit is
transmitted after the output value.
One period of the input signal is internally divided into
eight segments. The following segments [45°..90°,
90°..135°, 135°..180° etc. to 360°] are mapped on the
first segment [0°..45°]. The resulting output resolution
thus amounts to 8 times that of the TAN D/A con-
verter.
The converter resolution per segment can be set to all
whole-number values between 17 and 32. Subreso-
lutions result only if every nth subdivision is used. A
further decrease is possible by effecting a right shift by
n-bit of the output value.
In this mode, pin SDA can be used as serial data in-
put. The data read in here at the beginning of the data
transmission is output after the error bit.
The following table shows all possible settings and
resulting resolutions. With equal values, settings with
more favorable characteristics are shown in bold type.
A cyclic read out can be achieved by linking NWR to
SDA. A one is output after the error bit as a stop bit.
To store the output value for a new data transmission,
an interval of at least 64 clock pulses must be main-
tained at the clock input.
Fig. 11: synchronous-serial data transmission.
3. Incremental mode
Here, every change of angle with respect to the set
resolution is signaled as a change in output on track
DO(AX) or D1(BX). The square-wave signals prod-
uced have a phase shift of plus or minus 90°, depen-
ding on the direction of rotation.
In addition, the input signals are compared to refer-
ence voltage VREF and output to pins D3(A4) and
D4(B4). This corresponds to a resolution of four.
The zero signals, suitably prepared, are available at
pins D2(ZX) and D5(Z4). A direction signal is also
output to D6(ROT) and signals AX and BX are EX-OR-
gated at D7(AXB).
Incremental mode can be emulated in parallel-abso-
lute mode by reading address 4.