IC-JRX Datasheet, PDF (9/23 Pages) IC-Haus GmbH – µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 9/23
Input Register (read only)
reading of inputs / output feedback
Add.: 0
reset entry: 00h
Bit
7
6
5
4
3
2
1
0
Name
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
Bit 7..0
0
Input/Output IOx reads '0'
(r)
IN7..0
1
Input/Output IOx reads '1'
INx indicates the state for IOx (via I/O filter or bypass).
Change-of-input Message (read only)
for I/O stages in input mode
Bit
Name
7
DCH7
6
DCH6
5
DCH5
4
DCH4
3
DCH3
2
DCH2
Add.: 1
reset entry: 00h
1
DCH1
0
DCH0
Bit 7..0
0
DCH7..0
1
No change of state at the input IOx or no interrupt enable
(r)
Input IOx has had a change of state enabled for interrupt messages
Read access gates off changes to the register; the register is reenabled only when reset via EOI. Any
successive interrupts which occur during the read-out phase and before a reset with EOI are trapped by an
interrupt pipeline. If this happens, the message at INTN cannot be deleted by EOI, i.e. INTN constantly
remains on low. In this instance, EOI fills the change-of-input message from the pipeline.
Status bits can also be selectively deleted by disabling and reenabling IENx.
‘0’ is output for IOx pins in output mode.