IC-JRX Datasheet, PDF (17/23 Pages) IC-Haus GmbH – µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 17/23
ELECTRICAL CHARACTERISTICS
Operating Conditions: VCCD= VCCA= 5V ±10%, VB= 19.2..25.2V,
GNDA= GNDD= PGND= 0V, all inputs wired (to hi respectively to lo), Tj= 0..125EC unless otherwise noted.
Item Symbol Parameter
Conditions
Tj Fig.
Unit
°C
Min. Typ. Max.
µP Interface, I/O Logic, Frequency Divider, Interrupt (cont‘d)
710 Vc()hi
ESD Clamp Voltage hi at
Vc()hi= V() -VCCD; D0..7 with
CSN, WRN, RDN, A0..4, RESN, input function, I()= 20mA
CLK, BLFQ, D0..7, INTN
0.4
1.5
V
711 Vc()lo
ESD Clamp Voltage lo at
D0..7 with input function,
CSN, WRN, RDN, A0..4, RESN, I()= -20mA
CLK, BLFQ, D0..7, INTN
-1.5
-0.4
V
Input POE
F01 Vt()hi Threshold Voltage hi
2.2
V
F02 Vt()lo Threshold Voltage lo
0.8
V
F03 Vt()hys Hysteresis
Vt()hys= Vt()hi -t()lo
300
mV
F04 Rpd() Pull-Down Resistor
24
72
kΩ
F05 tw()lo Disable/Enable Pulse Width
1000
ns
F06 tsup()
F07 td(POE-
IOx)
Permissible Interference Pulse
Width
Power Output Switch-off Delay
POE: hi6lo until IOx disabled,
ie. V(IOx)< 80% (VB -Vs(IOx)hi),
RL= 240Ω..1kΩ
100
ns
5
µs
F08 Vc()hi ESD Clamp Voltage hi
Vc()hi= V(POE) -VCCA;
I(POE)= 20mA
0.8
2
V
F09 Vc()lo ESD Clamp Spannung lo
I(POE)= -20mA
-1.5
-0.4
V
Switching Characteristics
801 td()
Permissible Cycle Duration
at CLK
800
ns
802 tw()
Permis. Pulse Width lo at CLK
400
ns
803 td()
Permissible Cycle Duration
at BLFQ
100
ms
804 tw()
Permis. Pulse Width lo at BLFQ
50
ms
ELECTRICAL CHARACTERISTICS: WAVEFORMS
I
IOxpeak
I
IOxmax
Fig. 1: DC load
IOxdc
t
τ
t
T
Fig. 2: Pulse load, pulse duration 2 ms