IC-JRX Datasheet, PDF (22/23 Pages) IC-Haus GmbH – µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Pulse-width modulation
This function can be activated for any chosen I/O stage
in output mode.
First the duty cycle is determined via the PWM register
in 256 steps within one PWM period. Pulse direction
and the address for the desired driver stage is selected
via control word 5 (PWMPN, PWMADR2..0).
The PWM enable bit can now also be set via control
word 5. With this enable, the current source and any
active flash mode for the selected output are
automatically switched off.
The set duty cycle is activated when a new PWM
period is started.
A PWM signal is set at the selected output, whose
frequency is determined by the clock signal at CLK and
whose duty cycle follows the PWM register.
Rev A1, Page 22/23
The following correlations apply:
f_PWM
'
f_CLK
4096
;
∆t_PWM '
1
f_PWM × 256
;
Fig. 5: PWM signal form
t_PWMlo ' (PWMLEN %1) × ∆t_PWM
f_CLK
f_PWM
∆t_PWM
t_PWMlo
PWMLEN
: Clock frequency CLK
: frequency for the PWM signal at IOx
: Smallest possible pulse duration ‘lo’ (8 µs with a 2 MHz clock)
: pulse duration ‘lo’ (Iox = OFF with PWMPN = 1)
: Count pulse duration ‘lo’ stored in register PWM7..0
Selectable Pulse-Pause Ratios
PWM7..0
PWMPN Output signal
'00'h
0
Output stage "ON", Pin Iox = '1'
1
Output stage "OFF", Pin Iox = '0'
'01'h .. 'FE'h
'FF'h
0
Output pin IOx goes for (PWMLEN + 1) × ∆t_PWM to '0', and then for
(255 - PWMLEN) × ∆t_PWM to '1'
1
Output pin IOx goes for (PWMLEN + 1) × ∆t_PWM to '1', and then for
(255 - PWMLEN) × ∆t_PWM to '0'
0
Output stage "OFF", Pin Iox = '0'
1
Output stage "ON", Pin Iox = '1'
(reset entry)
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