IC-JRX Datasheet, PDF (7/23 Pages) IC-Haus GmbH – µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 7/23
Control Word 3 (flash pulse settings)
higher nibble
lower nibble
Bit
7
6
5
4
3
2
Name
NOBLFQ NOCLK PH1
PH0
-
-
Add.: 12
reset entry: 00h
1
0
PL1
PL0
higher nibble
Bit 7
0
Flash pulse is generated from the external clock signal at BLFQ
(r)
NOBLFQ
1
Flash Pulse is generated from clock signal CLK
Bit 6
0
Operation with the clock signal at CLK (all clock controlled actions are possible)
(r)
NOCLK
1
Operation without the clock signal at CLK (filtering etc. deactivated)
Bit 5..4
PH1..0
Flash frequency for I/O pins 4..7
PH1
PH0
NOBLFQ = 0
NOBLFQ = 1
0
0
0
1
1
0
1
1
f(BLFQ)
f(BLFQ) / 2
f(BLFQ) / 4
f(BLFQ) / 16
(r)
f(CLK) / 2¹⁹
f(CLK) / 2²⁰
f(CLK) / 2²¹
f(CLK) / 2²³
lower nibble
Bit 1..0
PL1..0
Flash frequency for I/O pins 0..3
PL1
PL0
NOBLFQ = 0
0
0
0
1
1
0
1
1
f(BLFQ)
f(BLFQ) / 2
f(BLFQ) / 4
f(BLFQ) / 16
(r)
NOBLFQ = 1
f(CLK) / 2¹⁹
f(CLK) / 2²⁰
f(CLK) / 2²¹
f(CLK) / 2²³
Control Word 4 (filter settings for overcurrent message)
Bit
7
6
5
4
3
2
Name
EOI
-
-
SCFH
BYPSCF -
Add.: 13
reset entry: 00h
1
0
-
SCFL
Bit 7
0
EOI
1
Bit 4
0
SCFH
1
Bit 3
0
BYPSCF
1
Bit 0
0
SCFL
1
No effect
(r)
"DELETE"s the interrupt message (change-of-input message; interrupt status register, overcurrent
message), accepts successive interrupts from the pipeline, deletes the message at INTN when the pipeline
is empty;
Bit automatically resets to '0'.
Overcurrent message with 2.3ms filtering (higher nibble)
(r)
Overcurrent message with 4.6ms Filtering (higher nibble)
Gives the filter times with the maximum clock frequency permitted at CLK, i.e. 1.25 MHz:
2.3ms from (2689.5 ± 192)× t(CLK) and
4.6ms from (5378.5 ± 384) × t(CLK) respectively
Filters for the overcurrent message are active
(r)
Bypass for the filters: overcurrent messages are reprocessed in their unfiltered state
Overcurrent message with 2.3 ms filtering (lower nibble)
(r)
Overcurrent message with 4.6 ms filtering (lower nibble)