IC-JRX Datasheet, PDF (19/23 Pages) IC-Haus GmbH – µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS

iC-JRX
µP INTERFACE WITH 2×4 24V HIGH-SIDE DRIVERS
Rev A1, Page 19/23
DESCRIPTION OF FUNCTIONS
iC-JRX is a bidirectional device which can analyze signals at the I/O pins and drive loads connected to ground.
The input and output modes can be set in blocks of 4 bits (using nibbles).
I/O stages in input mode pass on the external signal via digital filtering which can be switched off as required by
way of a bypass. Changes of level at any one input can generate an interrupt at the INTN port – providing that
messaging is enabled. Individually programmable low-side current sources are available for each pin, enabling
logic levels for the inputs to be defined (ranges 200 µA, 600 µA and 2 mA).
I/O stages in output mode can switch currents of up to 500 mA. A 200 µA high-side current source can be
activated to check the load for any interruptions. A PWM function and a flash mode for indicator lamps are
integrated in the device, both of which can be selected for any chosen output pin. If overcurrent is determined
at any of the outputs, caused for example by a short-circuit, this can be reported as an interrupt if suitably
enabled. If the device exceeds normal operating temperature, an interrupt gives a temperature warning; if,
following this, the device continues to overheat, the outputs are shutdown.
I/O stages in input mode
Input register (add. 0): reads the inputs
A hi level at IOx generates a hi signal at Dx. Any change to an input signal is accepted via digital filtering only
after the chosen filter time has ended. Doing this, the input comparator of each I/O stage switches the count
direction of a 3-bit counter. The counter output changes only when the final status is reached. The counters are
reset to a value of 3 by a lo signal at the RESN reset input. The counter is clocked externally via the CLK pin.
The scaling factor for the clock frequency and the input filter bypass can be programmed separately for both
nibbles (the bypass with BYPH or BYPL in control word 1). Switching the bypass permits operation without an
external clock signal (see below).
After the change-of-input message has been enabled (add. 8) a change of level at one of the I/O pins is signaled
via an interrupt to the microcontroller.
I/O stages in output mode
Input register (add. 0): reads the output feedback
A hi level at IOx generates a hi signal at Dx. Through this, the microcontroller can make a direct check of the
switching state and, in conjunction with the 200 µA high-side current source, can monitor the channel for any
cable fractures. As with the input read, the read-back signals can be reprocessed in their filtered or unfiltered
state.
Output register (add. 6): switches the various output stages on and off (for POE= 1)
Flash pulse enable (add. 7): enables flash mode
With this, each of the various output stages can be set to flash mode, providing the value of the corresponding
output register is ‘1’. The flash frequency is derived from BLFQ or, alternatively, can be generated from CLK (via
NOBLFQ in control word 3). Different flash frequencies can be set for both nibbles (ports 0..3 and 4..7).
PWM enable (add. 14)
A PWM signal for any chosen output stage can be activated with the aid of PWMEN in control word 5. The I/O
stage is selected using PWMADR2..0. PWMPN determines the direction of the PWM signal (active hi or active
lo). The shape of the PWM signal is given by the value of the PWM register (add. 15), multiplied by 16xtd(CLK).