HMT351U6MFR8C-S6 Datasheet, PDF (8/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
2.2 Input/Output Functional Description
Symbol
CK0–CK1
CK0–CK1
Type
SSTL
CKE0–CKE1 SSTL
S0–S1
SSTL
RAS, CAS, WE SSTL
ODT0–ODT1 SSTL
VREFDQ
VREFCA
Supply
Supply
VDDQ
Supply
BA0–BA2
SSTL
A0–A13
SSTL
DQ0–DQ63,
CB0–CB7
SSTL
DM0–DM8
SSTL
VDD, VSS
Supply
Polarity
Function
Differential
crossing
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl
inputs are sampled on the crossing of positive edge of CK and negative
edge of CK. Output (read) data is reference to the crossing of CK and CK
(Both directions of crossing).
Activates the SDRAM CK signal when high and deactivates the CK signal
Active High when low. By deactivating the clocks, CKE low initiates the Power Down
mode, or the Self Refresh mode.
Active Low
Enables the associated SDRAM command decoder when low and disables
the command decoder when high. When the command decoder is dis-
abled, new commands are ignored but previous operations continue. This
signal provides for external rank selection on systems with multiple ranks.
Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.
Active High
When high, termination resistance is enabled for all DQ, DQS, DQS and DM
pins, assuming this function is enabled in the Mode Register 1 (MR1).
Reference voltage for SSTL15 I/O inputs.
Reference voltage for SSTL 15 command/address inputs.
Power supply for the DDR3 SDRAM output buffers to provide improved
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ
shares the same power plane as VDD pins.
—
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row
address (RA0–RA15).
During a Read or Write command cycle, Address input defines the column
address. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-
—
charged. If AP is low, autoprecharge is disabled. During a Precharge com-
mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless
of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to
define which bank to precharge. A12(BC) is sampled during READ and
WRITE commands to determine if burst chop (on-the-fly) will be per-
formed (HIGH, no burst chop; LOW, burst chopped).
—
Data and Check Bit Input/Output pins.
Active High
DM is an input mask signal for write data. Input data is masked when DM
is sampled High coincident with that input data during a write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD
and VDDQ pins are tied to VDD/VDDQ planes on these modules.
Rev. 0.3 / Jan 2009
8