HMT351U6MFR8C-S6 Datasheet, PDF (32/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
I_{DD2N Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING;}
DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT
Signal: stable at 0; Pattern Details: see Table 5 on page 32
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
I_{DD2NT Address, Bank Address Inputs: partially toggling according to Table 6 on page 32; Data IO: FLOATING;}
DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT
Signal: toggling according to Table 6 on page 32; Pattern Details: see Table 6 on page 32
I_DDQ2NT Precharge Standby ODT IDDQ Current
(optional ^{Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current}
)
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
I_DD2P0 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power
Down Mode: Slow Exit^c)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
I_DD2P1 Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Precharge Power
Down Mode: Fast Exit^c)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
I_DD2Q
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0
I_DDQ4R Operating Burst Read IDDQ Current
(optional ^{Same definition like for IDD4R, however measuring IDDQ current instead of IDD current}
)
Rev. 0.3 / Jan 2009
32