HMT351U6MFR8C-S6 Datasheet, PDF (42/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
7. Electrical Characteristics and AC Timing
7.1 Refresh Parameters by Device Density
Parameter
REF command to
ACT or REF
command time
Average periodic
refresh interval
tREFI
Symbol
tRFC
512Mb 1Gb 2Gb 4Gb 8Gb Units
90
110 160 300 350
ns
0 ×C < T_CASE < 85 ×C
85 ×C < T_CASE < 95 ×C
7.8
7.8 7.8 7.8 7.8
ms
3.9
3.9 3.9 3.9 3.9 ms
7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC
for each corresponding bin
DDR3 800 Speed Bin
CL - nRCD - nRP
Parameter
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CL = 5
CWL = 5
CL = 6
CWL = 5
Supported CL Settings
Supported CWL Settings
Symbol
t_AA
t_RCD
t_RP
t_RC
t_RAS
t_CK(AVG)
t_CK(AVG)
DDR3-800E
6-6-6
min
max
15
20
15
—
15
—
52.5
—
37.5
9 * tREFI
Reserved
2.5
3.3
6
5
Unit Notes
ns
ns
ns
ns
ns
ns _1)2)3)4)
ns ₁₎₂₎₃₎
n_CK
n_CK
Rev. 0.3 / Jan 2009
42