HMT351U6MFR8C-S6 Datasheet, PDF (40/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

Table 9 - IDD5B Measurement-Loop Pattern^a)
HMT351U6MFR8C
HMT351U7MFR8C
Data^b)
00
REF 0 0 0 1 0 0 0 0 0 0 0
-
1 1.2
D, D 1 0 0 0 0 0 00 0 0 0 0
-
3,4
D, D 1 1 1 1 0 0 00 0 0 F 0
-
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.3 / Jan 2009
40