HMT351U6MFR8C-S6 Datasheet, PDF (33/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
Active Standby Current
I_DD3N
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers^b); ODT
Signal: stable at 0; Pattern Details: see Table 5 on page 32
Active Power-Down Current
I_DD3P
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
open; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0
Operating Burst Read Current
I_DD4R
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: High between RD;
Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 33; Data IO:
seamless read data burst with different data between one burst and the next one according to Table 7 on
page 33; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,...(see Table 7 on page 33); Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal:
stable at 0; Pattern Details: see Table 7 on page 33
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS: High between WR;
Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 34; Data IO:
I_{DD4W seamless read data burst with different data between one burst and the next one according to Table 8 on}
page 34; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,...(see Table 8 on page 34); Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal:
stable at HIGH; Pattern Details: see Table 8 on page 34
Burst Refresh Current
I_DD5B
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 26; BL: 8^a); AL: 0; CS: High between
REF; Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 35; Data
IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 35); Out-
put Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 9 on
page 35
Rev. 0.3 / Jan 2009
33