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HMT351U6MFR8C-S6 Datasheet, PDF (4/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs | |||
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HMT351U6MFR8C
HMT351U7MFR8C
1. Description
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 2Gb M version. DDR3 SDRAMs in Fine
Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 2Gb
M ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
⢠VDD=VDDQ=1.5V
⢠VDDSPD=3.3V to 3.6V
⢠Fully differential clock inputs (CK, /CK) operation
⢠Differential Data Strobe (DQS, /DQS)
⢠On chip DLL align DQ, DQS and /DQS transition with
CK transition
⢠DM masks write data-in at the both rising and falling
edges of the data strobe
⢠All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
⢠Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
⢠Programmable additive latency 0, CL-1, and CL-2 sup
ported
⢠Programmable CAS Write latency (CWL) = 5, 6, 7, 8
⢠Programmable burst length 4/8 with both nibble
sequential and interleave mode
⢠BL switch on the fly
⢠8banks
⢠8K refresh cycles /64ms
⢠DDR3 SDRAM Package: JEDEC standard 82ball
FBGA(x4/x8)) with support balls
⢠Driver strength selected by EMRS
⢠Dynamic On Die Termination supported
⢠Asynchronous RESET pin supported
⢠ZQ calibration supported
⢠TDQS (Termination Data Strobe) supported (x8 only)
⢠Write Levelization supported
⢠Auto Self Refresh supported
⢠On Die Thermal Sensor supported (JEDEC optional)
Rev. 0.3 / Jan 2009
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