HMT351U6MFR8C-S6 Datasheet, PDF (27/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
6.6 Pin Capacitance
Parameter
Symbol
DDR3-800
Min Max
DDR3-1066
Min
Max
DDR3-1333
Units Notes
Min Max
Input/output capacitance
(DQ, DM, DQS, DQS#, TDQS, C_IO
TBD TBD
TBD
TBD
TBD TBD pF 1,2,3
TDQS#)
Input capacitance, CK and
CK#
C_CK
TBD TBD
TBD
TBD
TBD TBD pF 2,3,5
Input capacitance delta
CK and CK#
C_DCK
TBD
TBD
TBD
TBD
TBD TBD pF 2,3,4
Input capacitance
(All other input-only pins)
C_I
TBD TBD
TBD
TBD
TBD TBD pF 2,3,6
Input capacitance delta, DQS
and DQS#
C_DDQS
TBD
TBD
TBD
TBD
TBD TBD pF 2,3,12
Input capacitance delta
(All CTRL input-only pins)
C_{DI_CTRL} TBD
TBD
TBD
TBD
TBD TBD pF 2,3,7,8
Input capacitance delta
C_{DI_ADD_ TBD}
TBD
TBD
TBD
2,3,9,
TBD TBD pF
(All ADD/CMD input-only pins) CMD
10
Input/output capacitance delta
(DQ, DM, DQS, DQS#)
C_DIO
TBD
TBD
TBD
TBD
TBD TBD pF 2,3,11
Notes:
1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic
characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied
(recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions,
the loading matches DQ and DQS.”)
2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of C_CK-C_CK#.
5. The minimum C_CK will be equal to the minimum C_I.
6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#.
7. CTRL pins defined as ODT, CS and CKE.
8. C_{DI_CTRL}=C_I(CNTL) - 0.5 * C_I(CLK) + C_I(CLK#))
9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#.
10. C_{DI_ADD_CMD}=C_I(ADD_CMD) - 0.5*(C_I(CLK)+C_I(CLK#))
11. C_DIO=C_IO(DQ) - 0.5*(C_IO(DQS)+C_IO(DQS#))
12. Absolute value of C_IO(DQS) - C_IO(DQS#)
Rev. 0.3 / Jan 2009
27