HMT351U6MFR8C-S6 Datasheet, PDF (24/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
Parameter
Symbol
Single-ended Output Slew Rate SRQse
DDR3-800
Min
Max
2.5
5
DDR3-1066
Min
Max
2.5
5
*** Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
For Ron = RZQ/7 setting
DDR3-1333
Min
Max
2.5
5
Units
V/ns
< Table 6.4.3: Output Slew Rate (single-ended) >
6.4.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and mea-
sured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4
Description
Differential output slew rate for rising edge
Measured
From
To
VOLdiff(AC) VOHdiff(AC)
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC)
Defined by
VOHdiff(AC)-VOLdiff(AC)
DeltaTRdiff
VOHdiff(AC)-VOLdiff(AC)
DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
D elta
T F d iff
D elta
T R d iff
vO H diff(AC)
O
vO Ldiff(AC)
< Figure 6.4.4: Differential Output Slew Rate Definition >
Rev. 0.3 / Jan 2009
24