HMT351U6MFR8C-S6 Datasheet, PDF (34/47 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM Unbuffered DIMMs

HMT351U6MFR8C
HMT351U7MFR8C
Self-Refresh Current: Normal Temperature Range
I_DD6
T_CASE: 0 - 85 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Normal^e);
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8^a); AL: 0; CS, Com-
mand, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: FLOATING
Self-Refresh Current: Extended Temperature Range (optional)^f)
T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Extend-
I_DD6ET ^{ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS,}
Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended
Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal:
FLOATING
Auto Self-Refresh Current (optional)^f)
T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Enabled^d);Self-Refresh Temperature Range (SRT): Normal^e);
I_{DD6TC CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Com-}
mand, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto Self-
Refresh operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: FLOATING
Operating Bank Interleave Read Current
I_DD7
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 26; BL:
8^a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially tog-
gling according to Table 10 on page 36; Data IO: read data burst with different data between one burst and
the next one according to Table 10 on page 36; DM: stable at 0; Bank Activity: two times interleaved
cycling through banks (0, 1,...7) with different addressing, wee Table 10 on page 36; Output Buffer and
RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 36
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported
by DDR3 SDRAM device
Rev. 0.3 / Jan 2009
34