HMT41GA7MFR8A Datasheet, PDF (7/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Symbol
DQ[63:0]
CB[7:0]
DM[8:0]
V_DD, V_SS
V_TT
DQS1[7:0]
DQS[7:0],
DQS[7:0]
SA[1:0]
SDA
SCL
EVENT
V_DDSPD
RESET
Par_in
Err_Out
Type Polarity
Function
I/O
—
Data and Check Input/Output pins.
IN
Supply
Supply
I/O
I/O
IN
I/O
IN
OUT
(open
drain)
Supply
IN
IN
OUT
(open
drain)
Active
High
Mask write data when high, issued concurrently with input data.
Power and ground for the DDR3 SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive
Edge
Positive line of the differential data strobe for input and output data
Negative
Edge
Negative line of the differential data strobe for input and output data
—
These signals are tied at the system planar to either V_SS or V_DDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
—
must be connected from the SDA bus line to V_DDSPD on the system planar to act as a
pullup.
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to V_DDSPD on the system planar to act as a pullup.
This signal indicates that a thermal event has been detected in the thermal sensing
Active Low device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register (72b-SD-RDIMM) and to
the RESET pin on the SDRAMs (all modules). When low, all register outputs will be
driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low
lever (the Clock Driver will remain synchronized with the input clock).
Parity bit for the Address and Control bus. (“1”: Odd, “0”: Even). Not used on 72b-SO-
DIMMs or 72b-SO-CDIMMs.
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to V on the system planner to act as a pull up. Not used on 72b-SO-
DIMMs or 72b-SO-CDIMMs.
Rev. 0.1 / Jul. 2012
7