HMT41GA7MFR8A Datasheet, PDF (29/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
CL - nRCD - nRP
Parameter
Internal read command to first data
Symbol
t_AA
DDR3L-800E
6-6-6
min
max
15
20
ACT to internal read or write delay time
t_RCD
15
—
PRE command period
t_RP
15
—
ACT to ACT or REF command period
t_RC
52.5
—
ACT to PRE command period
CL = 5
CL = 6
CWL = 5
CWL = 5
Supported CL Settings
Supported CWL Settings
t_RAS
t_CK(AVG)
t_CK(AVG)
37.5
9 * tREFI
3.0
3.3
2.5
3.3
5, 6
5
Unit
Notes
ns
ns
ns
ns
ns
ns
1,2,3,4,9,10
ns
1,2,3
n_CK
10
n_CK
Rev. 0.1 / Jul. 2012
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