HMT41GA7MFR8A Datasheet, PDF (43/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Table 5 - IDD2N and IDD3N Measurement-Loop Pattern^a)
Data^b)
00
1
2
3
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
D 100 0 0 0 0 0 0 0 0
-
D 1000 0 0 0 0 0 00
-
D 1111 0 0 0 0 0 F 0
-
D 1111 0 0 0 0 0 F 0
-
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern^a)
Data^b)
00
1
2
3
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
D 1000 0 0 0 0 0 0 0
-
D 1000 0 0 0 0 0 0 0
-
D 1111 0 0 0 0 0 F 0
-
D 1111 0 0 0 0 0 F 0
-
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.1 / Jul. 2012
43