HMT41GA7MFR8A Datasheet, PDF (5/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Pin Descriptions
Pin Name
Description
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
CAS
WE
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Num
ber
1
1
1
1
2
1
1
1
S[3:0] Chip Selects
4
A[9:0],A11,
A[15:13]
Address Inputs
14
A10/AP Address Input/Autoprecharge
1
A12/BC Address Input/Burst chop
1
BA[2:0] SDRAM Bank Addresses
3
SCL
Serial Presence Detect (SPD) Clock
Input
1
SDA SPD Data Input/Output
1
SA[1:0] SPD Address Inputs
2
Par_In
Parity bit for the Address and Control
bus
1
Err_Out
Parity error found on the Address
and Control bus
1
Pin Name
Description
ODT[1:0]
DQ[63:0]
CB[7:0]
DQS[8:0]
DQS[8:0]
DM[8:0]
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks
Num
ber
2
64
8
9
9
9
EVENT
Reserved for optional hardware
temperature event pin
1
RESET
V_DD
V_SS
V_REFDQ
V_REFCA
V_TT
V_DDSPD
Reset and SDRAM control pin
1
Power Supply
xx
Ground
xx
Reference Voltage for DQ
1
Reference Voltage for CA
1
Termination Voltage
2
SPD Power
1
Total : 204
Rev. 0.1 / Jul. 2012
5