HMT41GA7MFR8A Datasheet, PDF (37/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol
t_CK
CL
n_RCD
n_RC
n_RAS
n_RP
n_FAW
1KB page size
2KB page size
n_RRD
1KB page size
2KB page size
n_RFC -512Mb
n_RFC-1 Gb
n_RFC- 2 Gb
n_RFC- 4 Gb
n_RFC- 8 Gb
DDR3L-1066
7-7-7
1.875
7
7
27
20
7
20
27
4
6
48
59
86
139
187
DDR3L-1333
9-9-9
1.5
9
9
33
24
9
20
30
4
5
60
74
107
174
234
DDR3L-1600
11-11-11
1.25
11
11
39
28
11
24
32
5
6
72
88
128
208
280
Unit
ns
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
I_DD0
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8^a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
fer and RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
I_DD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8^a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 0.1 / Jul. 2012
37