HMT41GA7MFR8A Datasheet, PDF (6/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Input/Output Functional Descriptions
Symbol
CK0
CK0
CK1
CK0/CK0
CK1/CK1
CKE[1:0]
Type
IN
IN
IN
IN
IN
Polarity
Function
Positive
Edge
Positive line of the differential pair of system clock inputs that drives input to the on-
DIMM Clock Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAM on
rank 0 (72b-SD-DIMM).
Negative
Edge
Negative line of the differential pair of system clock inputs that drives input to the on-
DIMM Clock Driver (72b-SO-RDIMM), on-DIMM PLL (72b-SO-CDIMM), or to DRAM on
rank 0 (72b-SD-DIMM).
Positive
Edge
Positive line of a secondary differential pair of system clock inputs. Teminated but not
used on 72b-SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 or 72b-
SD-DIMMs.
Negative
Edge
Negative line of a secondary differential pair of system clock inputs. Teminated but not
used on 72b-SO-RDIMMs or 72b-SO-CDIMMs. Connected to DRAMs on rank 1 or 72b-
SD-DIMMs.
Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provieds PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank). Connected to the registering clock driver on 72b-SO-
RDIMMs, connected to DRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs.
S[1:0]
IN
ODT[1:0]
IN
RAS, CAS, WE
IN
V_REFDQ
V_REFCA
Supply
Supply
BA[2:0]
IN
A[9:0],
A10/AP,
A11,
IN
A12/BC
A[15:13]
Active
Low
Active
High
Active
Low
—
—
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
and previous operations continue. Connected to SDRAMs on 72b-SD-CDIMMs and 72b-
SO-DIMMs. For 72b-SO-RDIMMs, the combinations of these input signals perform
unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
On-Die Termination control signals. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-
SO-DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs.
When sampled at the positive rising edge of the clock. CAS, RAS, and WE define the
operation to be executed by the SDRAM. Connected to SDRAMs on 72b-SO-CDIMMs and
72b-SO-DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
Selects which SDRAM internal bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge commnad is being
applied. Bank address also derermines mode register is to be accessed during an MRS
cycle. Connected to SDRAMs on 72b-SO-CDIMMs and 72b-SO-DIMMs, connected to the
registering clock driver on 72b-SO-RDIMMs.
Provided the row address for Active commnads and the column address and Auto Pre-
charge bit for Read/Write commands to select one lacation out of the memory array in
the respective bank. A10 is sampled during a Precharge command to detemine whether
the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank
is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identifica-
tion for “BL on the fly” during CAS command. The address inputs also provied the op-
code during Mode Register Set commands. Connected to SDRAMs on 72b-SO-CDIMMs
and 72b-SO-DIMMs, connected to the registering clock driver on 72b-SO-RDIMMs.
Rev. 0.1 / Jul. 2012
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