HMT41GA7MFR8A Datasheet, PDF (24/48 Pages) Hynix Semiconductor – DDR3L SDRAM ECC SO-DIMMs Based on 4Gb M-die

Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output Slew Rate Definition
Description
Measured
From
To
Defined by
Differential output slew rate for rising edge
V_{OLdiff (AC)}
V_{OHdiff (AC)} [V_{OHdiff (AC)}-V_{OLdiff (AC)}] / DeltaTRdiff
Differential output slew rate for falling edge
Notes:
V_{OHdiff (AC)}
V_{OLdiff (AC)} [V_{OHdiff (AC)}-V_{OLdiff (AC)}] / DeltaTFdiff
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Delta
TRdiff
vOHdiff(AC)
O
Delta
TFdiff
vOLdiff(AC)
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
DDR3L-800 DDR3L-1066 DDR3l-1333
Parameter
Symbol Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 3.5 12 3.5 12 3.5 12
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
DDR3L-1600
Units
Min Max
3.5 12 V/ns
Rev. 0.1 / Jul. 2012
24