H27U518S2CTR-BC Datasheet, PDF (7/37 Pages) Hynix Semiconductor – 512 Mb NAND Flash

1.2 Pin Description
1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
Pin Name
Description
IO0-IO7
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
CLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE).
ADDRESS LATCH ENABLE
ALE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write
Enable (WE).
CE
CHIP ENABLE
This input controls the selection of the device.
WRITE ENABLE
WE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE.
READ ENABLE
RE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid tREA after the falling edge of RE which also increments the internal column address counter by
one.
WRITE PROTECT
WP
The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase)
operations.
R/B
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Vcc ¹
SUPPLY VOLTAGE
The Vcc supplies the power for all the operations (Read, Write, Erase).
Vss
GROUND
NC
NO CONNECTION
Table 2 : Pin Description
NOTE
1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during
program and erase operations.
Rev 1.0 / Dec. 2008
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