H27U518S2CTR-BC Datasheet, PDF (4/37 Pages) Hynix Semiconductor – 512 Mb NAND Flash

1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
1. SUMMARY DESCRIPTION
Hynix NAND H27U518S2C Series have 64 M × 8 bit with spare 2 M × 8 bit capacity. The device is offered in 3.3 V Vcc
Power Supply, and with x8 I/O interface.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The device is divided into blocks that can be erased independently so it is possible to preserve valid data while old data
is erased.
The device contains 4096 blocks, composed by 32 pages consisting in two NAND sturctures of 16 series connected Flash
cells. A program operation allows to write the 512-byte page in typical 200 us and an erase operation can be performed
in typical 1.5 ms on a 16 K-byte block.
Data in the page can be read out at 30 ns cycle time per byte. The I/O pins serve as the ports for address and data
input/output as well as command input. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, RE, ALE and CLE input pin. The on-chip
Program/Erase Controller automates all read, program and erase functions including pulse repetition, where required, and
internal verification and margining of data. The modify operations can be locked using the WP input. The output pin R/B
(open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B
pins can be connected all together to provide a global status signal.
The copy back function allows the optimization of defective blocks management. When a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial data
insertion phase.
Even the write-intensive systems can take advantage of the H27U518S2C Series extended reliability of 100K program/
erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE don’t
care function. This function allows the direct download of the code from the NAND Flash memory device by a microcon-
troller, since the CE transitions do not stop the read operation.
This device includes also extra features like OTP/Unique ID area, Read ID2 extension.
The H27U518S2C is available in 48-TSOP1 12 x 20 mm.
1.1 Product List
PART NUMBER
H27U518S2C
ORGANIZATION
x8
VCC RANGE
2.7 ~ 3.6 Volt
PACKAGE
48 TSOP 1
Rev 1.0 / Dec. 2008
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