H27U518S2CTR-BC Datasheet, PDF (14/37 Pages) Hynix Semiconductor – 512 Mb NAND Flash

1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
4. OTHER FEATURES
4.1 Power Up Sequence.
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal volt-
age detector disables all functions whenever Vcc is below V_LKO (1.8 V for 3.3 V version) . WP pin provides hardware pro-
tection and is recommended to be kept at V_IL during power-up and power-down. A recovery time of minimum 10 us is
required before internal circuit gets ready for any command sequences as shown in Figure 17. The two-step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-
back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset,
read, program, erase operation). It returns to high when the internal controller has finished the operation. The pin is an
open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/
B) and current drain during busy (I _busy), an appropriate value can be obtained with the following reference chart in Figure
18. Its value can be determined by the following guidance.
4.3 Data Protection
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal volt-
age detector disables all functions whenever Vcc is below VLKO (V_LKO=1.8V). The situation is described in Figure 21. The
two-step command sequence for program/erase provides additional software protection.
Rev 1.0 / Dec. 2008
14