H27U518S2CTR-BC Datasheet, PDF (19/37 Pages) Hynix Semiconductor – 512 Mb NAND Flash

1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
Parameter
Symbol
Min
Max Unit
CLE Setup time
CLE Hold time
CE setup time
CE hold time
WE pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE High hold time
Data Transfer from Cell to register
ALE to RE Delay (ID Read)
CLE to RE Delay
Ready to RE Low
RE Pulse Width
WE High to Busy
Read Cycle Time
RE Access Time
RE High to Output High Z
CE High to Output High Z
RE or CE high to Output hold
RE High Hold Time
Output High Z to RE low
WE High to RE low
Device Resetting Time (Read / Program / Erase)
Last RE High to BUSY (at sequential read)
CE High to Ready (in case of interception by CE)
CE High hold time (at the last serial read)
t_CLS
t_CLH
t_CS
t_CH
t_WP
t_ALS
t_ALH
t_DS
t_DH
t_WC
t_WH
t_R
t_AR1
t_CLR
t_RR
t_RP
t_WB
t_RC
t_REA
t_RHZ
t_CHZ
T_OH
T_REH
t_IR
t_WHR
t_RST
t_RB
t_CRY
t_CEH
15
ns
5
ns
20
ns
5
ns
15
ns
15
ns
5
ns
15
ns
5
ns
30
ns
10
ns
12
us
10
ns
10
ns
20
ns
15
ns
100
ns
30
ns
18
ns
30
ns
20
ns
10
10
ns
0
ns
60
ns
5/10/500 _us
(1,2)
100
ns
60+tr^{(1) ns}
100⁽³⁾
ns
Table 13 : AC Timing Characteristics
NOTE
1. The time to Ready depends on the value of the pull-up resistor tied to R/B pin.
2. If Reset Command (FFh) is issued at Ready state, the device goes into Busy for maximum 5 us.
3. To break the sequential read cycle. CE must be held high for a time longer than t_CEH
Rev 1.0 / Dec. 2008
19