H27U518S2CTR-BC Datasheet, PDF (12/37 Pages) Hynix Semiconductor – 512 Mb NAND Flash

1PrePreliminaryeee
H27U518S2C Series
512 Mbit (64 M x 8 bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address
loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block address loading
initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that mem-
ory contents are not accidentally erased due to external noise conditions.
The block address loading is accomplished three cycles. Only block addresses(Refer to Table 4 for further info) are need-
ed while A9 to A13 is ignored.
At the rising edge of WE after the erase confirm command input, the internal Program Erase Controller handles erase
and erase-verify. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 13 details
the sequence.
3.4 Copy-Back Program.
The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to another
page within the same plane without using an external memory. Since the time-consuming sequential-reading and its re-
loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a
block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for per-
forming a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with
the address of destination page. A normal read operation with "00h" command and the address of the source page moves
the whole 528byte data into the internal buffer. As soon as the device returns to Ready state, Page-Copy Data-input com-
mand (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h)
is not needed to actually begin the programming operation. For backward-compatibility, issuing Program Confirm com-
mand during copy-back does not prevent correct device operation.
Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished,
any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the same
between source and target page(Refer to Table 4 for details).
When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations
are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For
this reason, two bit error correction is recommended for the use of Copy-Back operation.
Figure 14 shows the command sequence for the copy-back operation.
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the read, program or erase operation is completed successfully. After writing 70h command to the
command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last (see figure Figure 8). This two-line control allows the system to poll the progress of each device in
multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated
status. Refer to Table 14 for specific Status Register definitions. The command register remains in Status Read mode until
further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command
(00h or 50h) should be given before sequential page read cycle.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad-
dress input of 00h. Two read cycles sequentially output the manufacturer code (ADh), the device code(76h). The command
register remains in Read ID mode until further commands are issued to it. Figure 15 shows the operation sequence, while
Tables 15 to 16 explain the byte meaning.
Rev 1.0 / Dec. 2008
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