HY29LV160 Datasheet, PDF (21/48 Pages) Hynix Semiconductor – 16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory

HY29LV160
Table 11. Write and Erase Operation Status Summary
Mode
Operation
DQ[7] ¹ DQ[6] DQ[5] DQ[3] DQ[2] ¹ RY/BY#
Programming in progress
DQ[7]# Toggle
0/1 ²
N/A
N/A
0
Programming completed
Normal
Erase in progress
Data
Data ⁴
Data
Data
Data
1
0
Toggle
0/1 ²
1³
Toggle
0
Erase completed ⁵
Data
Data ⁴
Data
Data
Data ⁴
1
Read within erase suspended
sector
1
No toggle
0
N/A
Toggle
1
Erase ^{Read within non-erase}
Suspend ^{suspended sector}
Data
Data
Data
Data
Data
1
Programming in progress ⁶
DQ[7]# Toggle
0/1 ²
N/A
N/A
0
Programming completed ⁶
Data
Data ⁴
Data
Data
Data
1
Notes:
1. A valid address is required when reading status information. See text for additional information.
2. DQ[5] status switches to a ‘1’ when a program or erase operation exceeds the maximum timing limit.
3. A ‘1’ during sector erase indicates that the 50 µs time-out has expired and active erasure is in progress.
applicable to the chip erase operation.
4. Equivalent to ‘No Toggle’ because data is obtained in this state.
5. Data (DQ[7:0]) = 0xFF immediately after erasure.
6. Programming can be done only in a non-suspended sector (a sector not specified for erasure).
DQ[3] is not
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is as-
serted low.
Figure 7 illustrates the Data# Polling test algorithm.
START
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
Test for DQ[7] = 1?
for Erase Operation
YES
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address, and is valid after the rising
edge of the final WE# pulse in the Program or
Erase command sequence, including during the
sector erase time-out. The system may use ei-
ther OE# or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode)
cause DQ[6] to toggle. DQ[6] stops toggling when
the operation is complete. If a program address
falls within a protected sector, DQ[6] toggles for
approximately 1 µs after the program command
sequence is written, then returns to reading array
data.
NO
NO
DQ[5] = 1?
YES
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
(Note 2)
Test for DQ[7] = 1?
for Erase Operation
YES
NO
PROGRAM/ERASE
EXCEEDED TIME ERROR
PROGRAM/ERASE
COMPLETE
Notes:
1. During programming , the program address. During sector erase , an
address within any non-protected sector specified for erasure. During
chip erase , an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously to DQ[5].
Figure 7. Data# Polling Test Algorithm
Rev. 1.2/May 01
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