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RFM42 Datasheet, PDF (96/110 Pages) –
RFM42/43
Register 71h. Modulation Mode Control 2
Bit
Name
Type
D7
D6
trclk[1:0]
R/W
D5
D4
dtmod[1:0]
R/W
Reset value = 00000000
D3
eninv
R/W
D2
fd[8]
R/W
D1
D0
modtyp[1:0]
R/W
Bit
7:6
5:4
3
2
1:0
Name
trclk[1:0]
dtmod[1:0]
eninv
fd[8]
modtyp[1:0]
Function
TX Data Clock Configuration.
00: No TX Data CLK is available (asynchronous mode – Can only work with
modulations FSK or OOK).
01: TX Data CLK is available via the GPIO (one of the GPIO‘s should be
programmed as well).
10: TX Data CLK is available via the SDO pin.
11: TX Data CLK is available via the nIRQ pin.
Modulation Source.
00: Direct Mode using TX_Data function via the GPIO pin (one of the GPIO‘s
should be programmed accordingly as well)
01: Direct Mode using TX_Data function via the SDI pin (only when nSEL is high)
10: FIFO Mode
11: PN9 (internally generated)
TX Data.
MSB of Frequency Deviation Setting, see "Register 72h. Frequency
Deviation".
Modulation Type.
00: Unmodulated carrier
01: OOK
10: FSK
11: GFSK (enable TX Data CLK (trclk[1:0]) when direct mode is used)
The frequency deviation can be calculated: Fd = 625 Hz x fd[8:0].
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