RFM42 Datasheet, PDF (71/110 Pages) –

RFM42/43
Register 30h. Data Access Control
Bit
Name
Type
D7
Reserved
R/w
D6
lsbfrst
R/w
D5
crcdonly
R/w
D4
Reserved
R/w
D3
enpactx
R/w
D2
encrc
R/w
D1
D0
crc[1:0]
R/w
Reset value = 10001101
Bit
Name
7
Reserved
6
lsbfrst
5
crcdonly
4
Reserved
3
enpactx
2
encrc
1:0
crc[1:0]
Function
Reserved.
LSB First Enable.
The LSB of the data will be transmitted first if this bit is set.
CRC Data Only Enable.
When this bit is set to 1 the CRC is calculated on the packet data fields only.
Reserved.
Enable Packet TX Handling.
If FIFO Mode (dtmod = 10) is being used automatic packet handling may be
enabled. Setting enpactx = 1 will enable automatic packet handling in the TX
path. Register 30–4D allow for various configurations of the packet structure.
Setting enpactx = 0 will not do any packet handling in the TX path. It will only
transmit what is loaded to the FIFO.
CRC Enable.
Cyclic Redundancy Check generation is enabled if this bit is set.
CRC Polynomial Selection.
00: CCITT
01: CRC-16 (IBM)
10: IEC-16
11: Biacheva
71
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