RFM42 Datasheet, PDF (52/110 Pages) –

RFM42/43
Register 03h. Interrupt/Status 1
Bit
Name
Type
D7
ifferr
R
D6
itxffafull
R
D5
ixtffaem
R
D4
Reserved
R
D3
iext
R
D2
ipksent
R
D1
Reserved
R
D0
Reserved
R
Reset value = xxxxxxxx
Bit
Name
7
ifferr
6
itxffafull
5
itxffaem
4
Reserved
3
iext
2
ipksent
1:0
Reserved
Function
FIFO Underflow/Overflow Error.
When set to 1 the TX FIFO has overflowed or underflowed.
TX FIFO Almost Full.
When set to 1 the TX FIFO has met its almost full threshold and needs to be
transmitted.
TX FIFO Almost Empty.
When set to 1 the TX FIFO is almost empty and needs to be filled.
Reserved.
External Interrupt.
When set to 1 an interrupt occurred on one of the GPIO‘s if it is programmed so. The
status can be checked in register 0Eh. See GPIOx Configuration section for the details.
Packet Sent Interrupt.
When set to1 a valid packet has been transmitted.
Reserved.
When any of the Interrupt/Status 1 bits change state from 0 to 1 the device will notify the microcontroller by setting the
nIRQ pin LOW if it is enabled in the Interrupt Enable 1 register. The nIRQ pin will go to HIGH and all the enabled
interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in the
Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and will not be
cleared by reading the register.
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