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RFM42 Datasheet, PDF (53/110 Pages) –
RFM42/43
Table 18. Interrupt or Status 1 Bit Set/Clear Description
Status
Bit
Name
Set/Clear Conditions
7
ifferr
Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset.
Set when the number of bytes written to TX FIFO is greater than the Almost Full
6
itxffafull
threshold. Automatically cleared at the start of transmission when the number of
bytes in the FIFO is less than or equal to the threshold.
Set when the number of bytes in the TX FIFO is less than or equal to the Almost
5
itxffaem
Empty threshold. Automatically cleared when the number of data bytes in the TX
FIFO is above the Almost Empty threshold.
4
Reserved Reserved.
3
iext
External interrupt source.
Set once a packet is successfully sent (no TX abort). Cleared upon leaving FIFO
2
ipksent
mode or at the start of a new transmission.
1:0
Reserved Reserved.
Table 19. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts?
Status
Bit
Name
Set/Clear Conditions
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO
7
ifferr
reset to the specific FIFO that caused the condition.
Will be set when the number of bytes written to TX FIFO is greater than the
Almost Full threshold set by SPI. It is automatically cleared when we start
6
itxffafull
transmitting and the FIFO data is read out and the number of bytes left in the
FIFO is smaller or equal to the threshold).
Will be set when the number of bytes (not yet transmitted) in TX FIFO is smaller
or equal than the Almost Empty threshold set by SPI. It is automatically cleared
5
itxffaem
when we write enough data to TX FIFO so that the number of data bytes not yet
transmitted is above the Almost Empty threshold.
4
Reserved Reserved.
3
iext
External interrupt source.
Will go high once a packet is sent all the way through (no TX abort). This status
2
ipksent
will be cleaned if 1) We leave FIFO mode or 2) In FIFO mode we start a new
transmission.
1:0
Reserved Reserved.
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