RFM42 Datasheet, PDF (30/110 Pages) –

RFM42/43
Add
08
7C
7D
Function/Descri
R/W
D7
ption
Operating &Function Reser
R/W
Control 2
ved
R/W TX FIFO Control 1
R/W TX FIFO Control 2
D6
Reser
ved
D5
D4
Reserve Reserve
d
d
txafthr[5] txafthr[4]
txafthr[5] txafthr[4]
D3
D2
autotx Reserve
d
txafthr[3] txafthr[2]
txafthr[3] txafthr[2]
D1
D0
Reserved
ffclrtx
txafthr[1]
txafthr[1]
txafthr[0]
txafthr[0]
POR
Def.
00h
37h
04h
The TX FIFO may be cleared or reset with the ffclrtx bit in ―Register 08h. Operating Mode and Function Control 2,‖. All
interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and ―Register 06h.
Interrupt Enable 2,‖. If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the
bits will still be read correctly in the Interrupt Status registers.
6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the TX mode. "Register 30h. Data Access
Control" through ―Register 3Eh. Packet Length,‖ control the configuration for Packet Handling. The usual fields for
network communication (such as preamble, synchronization word, headers, packet length, and CRC) can be
configured to be automatically added to the data payload. The fields needed for packet generation normally change
infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly
reduces the amount of communication between the microcontroller and the RFM42/43 and therefore also reduces the
required computational power of the microcontroller.
The general packet structure is shown in Figure 11. The length of each field is shown below the field. The preamble
pattern is always a series of alternating ones and zeroes, starting with a one. All the fields have programmable lengths
to accommodate different applications. The most common CRC polynominals are available for selection.
Figure 11. Packet Structure
An overview of the packet handler configuration registers is shown in Table 12. A complete register description
can be found in ―11.1. Complete Register Table and Descriptions‖.
6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field before
returning to ready mode and asserting the packet sent interrupt. To resume sending data from the FIFO the
microcontroller needs to command the module to re-enter TX mode Figure 12 provides an example transaction
where the packet length is set to three bytes.
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