RFM42 Datasheet, PDF (8/110 Pages) –

RFM42/43
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Parameter
Rise Time
Fall Time
Input Capacitance
Symb
ol
TRISE
Conditions
0.1 x VDD to 0.9 x VDD, CL= 5 pF
Min
—
TFALL 0.9 x VDD to 0.1 x VDD, CL= 5 pF —
CIN
—
Typ Max Units
—
8
ns
—
8
ns
—
1
pF
Logic High Level Input Voltage
Logic Low Level Input Voltage
Input Current
Logic High Level Output Voltage
Logic Low Level Output Voltage
VIH
VIL
IIN
VOH
VOL
VDD – 0.6 — —
V
— 0.6 V
0<VIN< VDD
–100
— 100 nA
IOH<1 mA source, VDD=1.8 V VDD – 0.6 — —
V
IOL<1 mA sink, VDD=1.8 V —
— 0.6 V
Note: All specification guaranteed by production test unless otherwise noted.
Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter
Symbol
Conditions
Min
Typ Max Units
Rise Time
Fall Time
Input Capacitance
TRISE
0.1 x VDD to 0.9 x VDD,
CL= 10 pF, DRV<1:0>=HH
—
TFALL
0.9 x VDD to 0.1 x VDD,
—
CL= 10 pF, DRV<1:0>=HH
CIN
—
—
8
ns
—
8
ns
—
1
pF
Logic High Level Input Voltage
VIH
VDD – 0.6 —
V
Logic Low Level Input Voltage
VIL
—
— 0.6 V
Input Current
IIN
0<VIN< VDD
–100
— 100 nA
Input Current If Pullup is
IINP
Activated
VIL=0 V
5
— 25
Maximum Output Current
IOmaxLL
DRV<1:0>=LL
0.1
0.5 0.8 mA
IOmaxLH
DRV<1:0>=LH
0.9
2.3 3.5 mA
IOmaxHL
DRV<1:0>=HL
1.5
3.1 4.8 mA
IOmaxHH
Logic High Level Output Voltage
VOH
DRV<1:0>=HH
IOH< IOmax source,
VDD=1.8 V
1.8
3.6 5.4 mA
VDD – 0.6 —
—
V
Logic Low Level Output Voltage
VOL IOL< IOmax sink, VDD=1.8 V
—
— 0.6 V
Note: All specification guaranteed by production test unless otherwise noted.
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