HD66740 Datasheet, PDF (77/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
80-system Bus Interface Timing Characteristics
(Vcc = 1.8 to 2.7 V)
Item
Symbol Min
Bus cycle time
Write t_CYCW
600
Read t_CYCR
800
Write low-level pulse width
PW_LW 120
Read low-level pulse width
PW_LR 350
Write high-level pulse width
PW_HW 300
Read high-level pulse width
PW_HR 300
Write/Read rise/fall time
t , _{WRr WRf}
—
Setup time (RS to CS*, WR*, RD*)
t _AS
50
Address hold time
t _AH
20
Write data setup time
t _{D SW}
60
Write data hold time
t_H
20
Read data delay time
t _DDR
—
Read data hold time
t _DHR
5
Typ Max Unit
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
— 25 ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
— 300 ns
—
—
ns
Test Condition
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
(Vcc = 2.7 to 3.6 V)
Item
Symbol Min
Bus cycle time
Write t_CYCW
380
Read t_CYCR
500
Write low-level pulse width
PW_LW
70
Read low-level pulse width
PW_LR 250
Write high-level pulse width
PW_HW 150
Read high-level pulse width
PW_HR 150
Write/Read rise/fall time
t_{WRr, WRf}
—
Setup time (RS to CS*, WR*, RD*)
t _AS
50
Address hold time
t _AH
20
Write data setup time
t _DSW
60
Write data hold time
t_H
20
Read data delay time
t _DDR
—
Read data hold time
t _DHR
5
Typ Max Unit
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
— 25 ns
—
—
ns
—
—
ns
—
—
ns
—
—
ns
— 200 ns
—
—
ns
Test Condition
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
Figure 48
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