HD66740 Datasheet, PDF (38/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
a) Basic Data-transfer Timing through Clock-synchronized Serial Bus Interface
Transfer start
Transfer end
CS*
(Input)
SCL
(Input)
SDA
(Input/
output)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
LSB
"0" "1" "1" "1" "0" ID RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Device ID code
RS R/W
Start byte
Instruction, RAM data
b) Consecutive Data-transfer Timing through Clock-synchronized Serial Bus Interface
CS*
(Input)
SCL
(Input)
12 345 678
SDA
(Input/
output)
Start
Start byte
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Instruction 1
Instruction 2
Instruction 3
Instruction 1
Instruction 2
End
execution time
execution time
Note: When instruciton 1 is a clear display instruction, adjust the transfer rate so that the 8th bit of instruction 2
is transferred after execution of the clear display instruction.
c) RAM Data Read-transfer Timing
CS*
(Input)
SCL
(Input)
12 345 678
SDA
(Input/
output)
Start
Start byte
RS = 1, R/W = 1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Dummy read 1
Dummy read 2
RAM data read 1
End
Note: Two bytes of the RAM read data after the start byte are invalid. The HD66740 starts to read the correct
RAM data from the third byte.
Figure 16 Clock-synchronized Serial Interface Timing Sequence
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