HD66740 Datasheet, PDF (40/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
a) Basic data-receive timing through the I2C bus interface
Transfer start
Transfer end
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
SCL
(input)
SDA
(input/
output)
"0" "1" "1" "1" "0" ID RS "0" Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Device ID code
RS RW
Start byte
Acknowledge Instruction / RAM data Acknowledge
b) Consecutive data-receive timing through the I2C bus interface
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
SDA ^S
Start byte
Transfer start
Instruction or
RAM write
Instruction or
RAM write
Instruction or
RAM write
Instruction or
RAM write
P
Transfer end
Instruction / RAM
write execution.
note:
- Start byte should be transfered just after start (S).
Instruction / RAM
write execution.
Instruction / RAM
write execution.
Instruction / RAM
write execution.
Figure 16-a I2C bus interface data-receive sequence
a) Basic data-send timing through the I2C bus interface
Transfer start
Transfer end
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
SCL
(input)
SDA
(input/
output)
"0" "1" "1" "1" "0" ID "1" "1" Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack
Device ID code
RS RW
Start byte
Acknowledge
RAM read
Acknowledge
b) Consecutive data-send timing through the I2C bus interface
SCL
SDA ^S
Start byte
Transfer start
Dummy read
(1 byte)
note:
- Start byte should be transfered just after start (S).
RAM data read
RAM data read
RAM data read
P
Transfer end
Figure 16-b I2C bus interface data-send sequence
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