HD66740 Datasheet, PDF (30/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
RAM Address Set
AD10-0: Initially set RAM addresses to the address counter (AC). Once the RAM data is written, the
AC is automatically updated according to the I/D bit. This allows consecutive accesses without
resetting addresses. Once the RAM data is read, the AC is automatically updated according to the I/D
bit when RDM = 0, and not updated when RDM = 1. Set RDM to 1 when read, modify, and write are
done in every one-byte data. RAM address setting is not allowed in the sleep mode or standby mode.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 0 1 AD10 AD9 AD8 AD7 AD6
0 0 1 1 AD5 AD4 AD3 AD2 AD1 AD0
Figure 12 RAM Address Set Instruction
Table 13 AD Bits and CGRAM Settings
AD10–AD0
"000"H–"06F"H
"080"H–"0EF"H
"100"H–"16F"H
"180"H–"1EF"H
"200"H–"26F"H
"280"H–"2EF"H
"300"H–"36F"H
"380"H–"3EF"H
"400"H–"46F"H
"480"H–"4EF"H
CGRAM Setting
Bit map data for COM1 to COM8
Bit map data for COM9 to COM16
Bit map data for COM17 to COM24
Bit map data for COM25 to COM32
Bit map data for COM33 to COM40
Bit map data for COM41 to COM48
Bit map data for COM49 to COM56
Bit map data for COM57 to COM64
Bit map data for COM65 to COM72
Bit map data for COM73 to COM80
Write Data to RAM
WD7-0 : Write 8-bit data to the CGRAM. After a write, the address is automatically incremented or
decremented by 1 according to the I/D bit setting. During the sleep and standby modes, the CGRAM
cannot be accessed.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
Figure 13 Write Data to RAM Instruction
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