HD66740 Datasheet, PDF (24/95 Pages) Hitachi Semiconductor – 112 x 80-dot Graphics LCD Controller/Driver

HD66740
Display Line Control
NL3-0: Set NL2–NL0 bits when SW = 0, and the NL3 bit when SW = 1 to specify the display lines.
Display lines change the liquid crystal display drive duty ratio. CGRAM address mapping does not
depend on the number of display lines.
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
NL2 NL1 NL0 (SW = 0)
CN1 CN0 NL3 (SW = 1)
Figure 8 Display-line Control Instruction
Table 9 NL Bits and Display Lines
Graphics
NL3 NL2 NL1 NL0 Display
0 0 0 0 112 x 8 dots
0 0 0 1 112 x 16 dots
0 0 1 0 112 x 24 dots
0 0 1 1 112 x 32 dots
0 1 0 0 112 x 40 dots
0 1 0 1 112 x 48 dots
0 1 1 0 112 x 56 dots
0 1 1 1 112 x 64 dots
1 0 0 0 112 x 72 dots
1 0 0 1 112 x 80 dots
LCD Drive
Duty
1/8 Duty
1/16 Duty
1/24 Duty
1/32 Duty
1/40 Duty
1/48 Duty
1/56 Duty
1/64 Duty
1/72 Duty
1/80 Duty
Common
Driver Used
COM1–COM8
COM1–COM16
COM1–COM24
COM1–COM32
COM1–COM40
COM1–COM48
COM1–COM56
COM1–COM64
COM1–COM72
COM1–COM80
CN1–CN0: Set CN1–CN0 bits when SW = 1. When CN1–0 = 01, the display position is shifted by 16
dots below and display starts from COM17. When the liquid crystal is driven at low duty in the system
wait state, it can display partially at the center of the screen. For details, see the Partial-display-on
Function section.
When CN1–CN0 = 10, the display position is shifted by 8 dots above and second-line display starts from
COM1. The 8 dots of the first line are moved to the lowest edge of the display screen. The output
position of the lowest edge depends on the drive duty setting. In vertical smooth scrolling, PS1–PS0
bits can selectively fixed-display only the first to the third lines. Combining these functions enables the
fixed display of one line of the lowest edge. For details, see the Partial Smooth Scroll Display Function
section.
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